The Longnail High-Level Synthesis system translates abstract descriptions of the semantics of custom instructions formulated in CoreDSL 2.0 into actual hardware-blocks in RTL. 

The SCAIE-V interface is a portable interface for extending RISC-V core with custom instructions. It applies to both pipelined and non-pipelined core. The custom instructions supported do not just cover Register-type instructions, but also extend to custom control flow (jumps, branches) and custom memory operations. SCAIE-V supports executing complex custom instructions more efficiently by decoupling their execution from the base processor, and automatically inserting the required hazard handling logic to guarantee their correct interoperation with regular RISC-V instructions.

Figure: Speculative program execution can enable side channel

Moonlight is a subsystem around a TGC core developed by MINRES. The Good Core (TGC) [1] is a highly flexible, scalable and expandable RISC-V processor core and the TGC variant to be used in the subsystem is configurable.

Moonlight contains a configurable APB3 subsystem with a customizable number of different peripherals, e.g., GPIO, UART, Timer, SPI, I2S Receiver, DMA.

The QEMU Timing Analyzer (QTA) is a QEMU plugin which extends QEMU for the time annotated execution of binary programs. QTA has been tested only for RISC-V and TriCore. As the implementation extends QEMU through TCG plugin API it should be compatible with any other ISA and all future QEMU versions . QTA comes with a frontend that can import output files from AbsInt aiT WCET analysis.

We introduce muRISCV-NN, an open-source compute library for embedded and microcontroller class systems. muRISCV-NN targets to provide an open-source, and vendor-agnostic compute library targeting all RISC-V-compliant platforms for supplying a HW/SW interface between industry-standard deep learning libraries and emerging ultra-low-power compute platforms. Forked from ARM’s CMSIS-NN library, muRISCV-NN provides optimized scalar kernels written in plain C as an efficient and highly portable baseline.

The eVerify framework supports formal software verification by considering the hardware behavior of loosely coupled devices, e.g., peripherals.

This is achieved using the Behavioral Description (BD) based on CTL* to specify hardware behavior from the software point of view. Based on the BD specification, the tool verifyDown generates assumptions/assertions for the hardware description and the software driver code.

The CDR is a an analog ecosystem component that implements in a high speed serial data input interface. The CDR extracts clock information from the serial data stream and retimes the data. Combined with deserializers & serializers it provides high speed memory I/O access of several Gbps. In first designs the CDR applies NRZ coding validated in 22FDX and IHP 130nm technology. Later designs will be optimize for PAM4 encodings.

The PLL is a component of the Scale4Edge ecosystem that generates a high frequency clock output (>1 Ghz) from a low frequency clock input signal. The output frequency is a scalable multiple of the input frequency and configurable at runtime. The  PLL was designed with analog subcomponents in a first step. It will be optimized at system level as a synthesizable digital PLL in further steps. The designs are mainly validated by tapeouts in 22FDX technology.

The Ecosystem microcontroller is a PULPissimo-based microcontroller featuring the following Scale4Edge ecosystem IPs:

• A RISC-V TGC processor core
• The AI hardware accelerator UltraTrail
• A phase-locked loop (PLL)

Due to the high configurability of the individual components, the platform can be quickly and easily adapted to specific applications. A specialized ecosystem microcontroller was taped-out in 22nm FDSOI technology as a demonstrator for an audio event detection use-case provided by the project partner Bosch.