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FreiTest (developed from PHAETON) is an ATPG (Automatic Test Pattern Generation) Framework based on SAT-Solving (Boolean Satisfiability Problem) and BMC (Bounded Model Checking). It generates full-scan / sequential test patterns and Software-Based Self-Tests (SBSTs) for synthesized circuits using the Validity Checker Module (VCM) specification mechanism.
Links
Visibility
Publicly available!
ISA Compliance
Supported Bus Protocols
Status
Date of Availability
Contact
Universität Freiburg
Tobias Faller
Georges-Köhler-Allee 051
79106 Freiburg
Deutschland
Contact Email
fallert [at] informatik.uni-freiburg.de
Target TRL at the end of phase 1
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle
Component is required for safety critical systems
Ja
Category
Software-Based Self-Test (SBST)