SCAIE-V Scalable ISA Extension Interface for RISC-V Cores

The SCAIE-V interface is a portable interface for extending RISC-V core with custom instructions. It applies to both pipelined and non-pipelined core. The custom instructions supported do not just cover Register-type instructions, but also extend to custom control flow (jumps, branches) and custom memory operations. SCAIE-V supports executing complex custom instructions more efficiently by decoupling their execution from the base processor, and automatically inserting the required hazard handling logic to guarantee their correct interoperation with regular RISC-V instructions.

The technology has been demonstrated on a number of processors, reaching from non-commercial (e.g., VexRiscv, CVA5, CVA6, ...) to commercial cores (MINRES TGC family).

SCAIE-V forms the target of the Longnail High-Level Synthesis system that can create the actual hardware for the custom instructions from abstract descriptions in the CoreDSL 2.0 language.