F - Single-Precision Floating-Point

An RTL processor implementation can be verified using our co-simulation approaches, which compares the implementation with a functional reference model. As a functional reference model, an instruction set simulator (ISS) that is part of the open-source RISC-V VP can be used. Our cross-level processor verification approach generates endless instruction streams and tightly integrates the ISS with the RTL core with the aid of in-memory communication. The setup allows restriction-free instruction generation, enabling a comprehensive testing approach.

FEAR-V is a fast scalable simulation and analysis framework for RISC-V architectures based on QEMU. The generation, simulation, and analysis can be scaled by ISA configuration as well as n-bit permanent and transient faults. The fault injection covers GPR, CSR, instruction, and memory analysis.

FreiTest (developed from PHAETON) is an ATPG (Automatic Test Pattern Generation) Framework based on SAT-Solving (Boolean Satisfiability Problem) and BMC (Bounded Model Checking). It generates Test Patterns and Software-Based Self-Tests (SBSTs) for synthesized circuits and is under active development. First results on achieved Fault Coverages have been published on the IEEE ETS2023 conference in Venice under the title "Constraint-Based Automatic SBST Generation for RISC-V Processor Families".

PikeOS and PikeOS for MPU are each a real-time operating system and hypervisor for embedded systems. It provides partitioning to separate different applications or guest operating systems from each other. PikeOS is often combined with ELinOS, SYSGO's embedded Linux, which is then run in a partition under the PikeOS hypervisor.

The Extensible Compiler provides an LLVM-based toolchain to develop C/C++/Assembly programs for RISC-V. It is designed to easily accommodate custom extensions to the RISC-V ISA by supporting the Scale4Edge developed CoreDSL for describing ISA extensions.

aiT automatically computes safe bounds for the worst-case execu­tion time of tasks in bina­ry execut­ables, taking into account the cache and pipe­line behavior of the processor in question.

StackAnalyzer automatically determines the worst-case stack usage of the tasks in embed­ded applications. It directly ana­lyzes binary execut­ables and considers all possible execution scenarios.

An extensible and configurable RISC-V based Virtual Prototype (VP) implemented in SystemC TLM. The feature set includes support for the RV32GC and RV64GC ISA, privilege levels (M,S,U), virtual memory, SW debug via Eclipse, a HiFive1 configuration and several operating systems including Linux. At UB the RISC-V VP serves as platform for several different research directions (visit https://agra.informatik.uni-bremen.de/projects/risc-v/ for further information and the most recent updates).

ETISS is a C++ ISS (Instruction Set Simulator), which is designed to simulate instructions for a target core on a host computer. It translates binary instructions into C code and appends translated code into a block, which will be compiled and executed at runtime. As aforementioned, it is Extendable, thus it supports myriad level of customization by adopting the technique of plug-ins. ETISS supports varied Instruction Set Architectures (ISAs) according to user needs (see architecture models in ArchImpl/).

CompCert is a formally verified optimizing C compiler. It accepts most of the ISO-C 99 language, with some minor exceptions and a few useful extensions. Its intended use is the compilation of life-critical and mission-critical software written in C and meeting high levels of assurance.