SCAIE-V Scalable ISA Extension Interface for RISC-V Cores
The SCAIE-V interface is a portable interface for extending RISC-V core with custom instructions. It applies to both pipelined and non-pipelined core. The custom instructions supported do not just cover Register-type instructions, but also extend to custom control flow (jumps, branches) and custom memory operations. SCAIE-V supports executing complex custom instructions more efficiently by decoupling their execution from the base processor, and automatically inserting the required hazard handling logic to guarantee their correct interoperation with regular RISC-V instructions.
Apache 2.0
Hardware Architectures and EDA Tools for Creating and Integrating RISC-V ISA Extensions (ISAX Tools)
Instruction Set Architecture eXtensions (here abbreviated as ISAX), sometimes also known as Custom Instructions, are one of the key means to specialize a processor for a specific application domain. They enable, e.g., higher performance or better energy efficiency than realizing the applications using just the generic, general-purpose instruction set.
In Scale4Edge, TUDA works on three key technologies aiming to ease the development and deployment of ISAX:
SCAIE-V and CoreDSL have been open-sourced under a permissive license. Longnail remains proprietary to enable commercial exploitation after the end of Scale4Edge Phase 2.