TGC-VP

Based on years of experience developing and integrating SystemC based virtual platforms in the industry, MINRES has created DBT-RISE (Dynamic Binary Translation Re-targetable Instruction Set Simulator), a versatile environment to rapidly implement ISS of any architecture. DBT-RISE serves as basis for the implementation of the TGC (The Good Core) ISS (TGC-VP).

TGC-VP provides the following features:

• Easy to integrate into SystemC/TLM2.0 based virtual platforms
• Interpreted and compiled (just-in-time, JIT) execution
• Instruction accurate execution
• Loosely and approximately time accuracy
• Instruction accurate trap handling (exception and interrupt)
• Supported interfaces
  • Bus: SystemC TLM generic protocol (blocking, DMI), AHB, AXI
  • Interrupt, Reset, Clock: sc_signal, tick-less clock
• OCDS support (GDB RSP, MCD)
• Extendability via plugins
• Platform debug support
  • Disassembler trace as log and SCV trace
  • Transaction recording (based on SCV, with various database backends)
• Supported platforms
  • Any Linux 
  • Windows