Fault Effect Simulation and Analysis for RISC-V (FEAR-V)

FEAR-V is a fast scalable simulation and analysis framework for RISC-V architectures based on QEMU. The generation, simulation, and analysis can be scaled by ISA configuration as well as n-bit permanent and transient faults. The fault injection covers GPR, CSR, instruction, and memory analysis.

The framework comes with a SW library and a front-end for C source code program generation, which are compiled to RV32 target binaries of the specified ISA subset. Each SW binary is dynamically analyzed for its instruction, register, and memory execution coverage. After automatic mutant generation for fault simulation the different fault injected mutants are executed with exception, timeout, and signature violation error detection. A final optimization step with optional weights minimizes the set of SW programs with the same coverage.