Image
An extensible and configurable RISC-V based Virtual Prototype (VP) implemented in SystemC TLM. The feature set includes support for the RV32GC and RV64GC ISA, privilege levels (M,S,U), virtual memory, SW debug via Eclipse, a HiFive1 configuration and several operating systems including Linux. At UB the RISC-V VP serves as platform for several different research directions (visit https://agra.informatik.uni-bremen.de/projects/risc-v/ for further information and the most recent updates).
Links
Visibility
Publicly available!
License
MIT
ISA Compliance
Status
Contact
Universität Bremen
Rolf Drechsler
Bibliothekstr. 5
28359 Bremen
Deutschland
Contact Email
drechsler [at] uni-bremen.de
Target TRL at the end of phase 1
TRL3: Nachweis der Funktionsfähigkeit --> Plattform ohne Parametrisierbarkeit
Target TRL at the end of phase 2
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Component is required for safety critical systems
Nein
Category
RISC-V Virtual Prototype