X = ISA Extension (manuell)

Verification IP

Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL3: Nachweis der Funktionsfähigkeit --> Plattform ohne Parametrisierbarkeit
Target TRL at the end of phase 2
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung

An RTL processor implementation can be verified using our co-simulation approaches, which compares the implementation with a functional reference model. As a functional reference model, an instruction set simulator (ISS) that is part of the open-source RISC-V VP can be used. Our cross-level processor verification approach generates endless instruction streams and tightly integrates the ISS with the RTL core with the aid of in-memory communication. The setup allows restriction-free instruction generation, enabling a comprehensive testing approach.

Status
Visibility
Internal for Scale4Edge partners only!

SymEx-VP

Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL3: Nachweis der Funktionsfähigkeit --> Plattform ohne Parametrisierbarkeit
Target TRL at the end of phase 2
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung

SymEx-VP focuses explicitly on testing software for constrained embedded devices (e.g. as used in the Internet of Things). This software often interacts very closely with low-level hardware peripherals and in order to support these interactions, during simulation-based software testing, SymEx-VP supports SystemC peripheral models. SystemC is a C++ class library for modeling hardware peripherals.

Status
Visibility
Publicly available!

Hardware Architectures and EDA Tools for Creating and Integrating RISC-V ISA Extensions (ISAX Tools)

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ISAX Compiler Toolchain
Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Target TRL at the end of phase 2
TRL5: Versuchsaufbau in vereinfachter Einsatzumgebung --> Optimierte Plattform

Instruction Set Architecture eXtensions (here abbreviated as ISAX), sometimes also known as Custom Instructions, are one of the key means to specialize a processor for a specific application domain. They enable, e.g., higher performance or better energy efficiency than realizing the applications using just the generic, general-purpose instruction set.

In Scale4Edge, TUDA works on three key technologies aiming to ease the development and deployment of ISAX:

Status
License

SCAIE-V and CoreDSL have been open-sourced under a permissive license. Longnail remains proprietary to enable commercial exploitation after the end of Scale4Edge Phase 2.

Visibility
Internal for Scale4Edge partners only!

Extensible Compiler (X-LLVM, Seal5)

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Extensible Compiler
Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle

The Extensible Compiler provides an LLVM-based toolchain to develop C/C++/Assembly programs for RISC-V. It is designed to easily accommodate custom extensions to the RISC-V ISA by supporting the Scale4Edge developed CoreDSL for describing ISA extensions.

Status
License

Apache License 2.0

A permissive license whose main conditions require preservation of copyright and license notices. Contributors provide an express grant of patent rights. Licensed works, modifications, and larger works may be distributed under different terms and without source code.

Visibility
Publicly available!

aiT and StackAnalyzer for RISC-V

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Call graph with timing information from aiT
Call graph with stack usage from StackAnalyzer
Component is required for safety critical systems
Ja
Target TRL at the end of phase 1
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle

aiT automatically computes safe bounds for the worst-case execu­tion time of tasks in bina­ry execut­ables, taking into account the cache and pipe­line behavior of the processor in question.

StackAnalyzer automatically determines the worst-case stack usage of the tasks in embed­ded applications. It directly ana­lyzes binary execut­ables and considers all possible execution scenarios.

License

This distribution of aiT and StackAnalyzer can be used for evaluation and research within the Scale4Edge project, but not for commercial purposes (see also the license information in the installation packages). Evaluation licenses and commercial licenses can be obtained from AbsInt.

Visibility
Publicly available!