SCAIE-V Scalable ISA Extension Interface for RISC-V Cores
The SCAIE-V interface is a portable interface for extending RISC-V core with custom instructions. It applies to both pipelined and non-pipelined core. The custom instructions supported do not just cover Register-type instructions, but also extend to custom control flow (jumps, branches) and custom memory operations. SCAIE-V supports executing complex custom instructions more efficiently by decoupling their execution from the base processor, and automatically inserting the required hazard handling logic to guarantee their correct interoperation with regular RISC-V instructions.
Apache 2.0
aiT and StackAnalyzer for RISC-V
aiT automatically computes safe bounds for the worst-case execution time of tasks in binary executables, taking into account the cache and pipeline behavior of the processor in question.
StackAnalyzer automatically determines the worst-case stack usage of the tasks in embedded applications. It directly analyzes binary executables and considers all possible execution scenarios.
This distribution of aiT and StackAnalyzer can be used for evaluation and research within the Scale4Edge project, but not for commercial purposes (see also the license information in the installation packages). Evaluation licenses and commercial licenses can be obtained from AbsInt.