V - Vector Operations

muRISCV-NN

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muRISCV-NN Logo
Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL3: Nachweis der Funktionsfähigkeit --> Plattform ohne Parametrisierbarkeit
Target TRL at the end of phase 2
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung

We introduce muRISCV-NN, an open-source compute library for embedded and microcontroller class systems. muRISCV-NN targets to provide an open-source, and vendor-agnostic compute library targeting all RISC-V-compliant platforms for supplying a HW/SW interface between industry-standard deep learning libraries and emerging ultra-low-power compute platforms. Forked from ARM’s CMSIS-NN library, muRISCV-NN provides optimized scalar kernels written in plain C as an efficient and highly portable baseline.

Status
Visibility
Publicly available!

aiT and StackAnalyzer for RISC-V

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Call graph with timing information from aiT
Call graph with stack usage from StackAnalyzer
Component is required for safety critical systems
Ja
Target TRL at the end of phase 1
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle

aiT automatically computes safe bounds for the worst-case execu­tion time of tasks in bina­ry execut­ables, taking into account the cache and pipe­line behavior of the processor in question.

StackAnalyzer automatically determines the worst-case stack usage of the tasks in embed­ded applications. It directly ana­lyzes binary execut­ables and considers all possible execution scenarios.

Status
License

This distribution of aiT and StackAnalyzer can be used for evaluation and research within the Scale4Edge project, but not for commercial purposes (see also the license information in the installation packages). Evaluation licenses and commercial licenses can be obtained from AbsInt.

Visibility
Publicly available!

ETISS - Extendable Translating Instruction Set Simulator

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ETISS logo
Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Target TRL at the end of phase 2
TRL5: Versuchsaufbau in vereinfachter Einsatzumgebung --> Optimierte Plattform

ETISS is a C++ ISS (Instruction Set Simulator), which is designed to simulate instructions for a target core on a host computer. It translates binary instructions into C code and appends translated code into a block, which will be compiled and executed at runtime. As aforementioned, it is Extendable, thus it supports myriad level of customization by adopting the technique of plug-ins. ETISS supports varied Instruction Set Architectures (ISAs) according to user needs (see architecture models in ArchImpl/).

Status
License

See file LICENSE inside GitHub Repo.

Visibility
Publicly available!