Debug Support - Privileged Level 4

On Chip Debug Hardware

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RISC-V Debug System Overview (Source: Figure 2.1 in RISC-V External Debug Support Version 0.13.2)
Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL5: Versuchsaufbau in vereinfachter Einsatzumgebung --> Optimierte Plattform
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle

Infineon implements for its evaluation platform in alignment with Partner Lauterbach specific Hardware Components for On-Chip-Debug. The Hardware acts as Evaluation Vehicle for the Lauterbach On Chip Debug solution.

Status
Planned
License

The Infineon Solution will be productized with its chips. It is therefore no tool or IP but part of semiconductor products.

Visibility
Internal for Scale4Edge partners only!

TGC Cores

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TGC Core
Component is required for safety critical systems
Ja
Target TRL at the end of phase 1
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle
Target TRL at the end of phase 2
TRL7: Demonstration des Systemprototyps in einer betrieblichen Umgebung

The Good Folk Series is a highly flexible, scalable and configurable RISC-V based core family developed by MINRES. The standard cores can easily be tailored to specific application requirements using CoreDSL.

It is technology independent, ensures integrity and targets low power edge computing applications. The comprehensive SDK and concise documentation makes it accessible to small and medium companies.

Status
Available
License

Send an email eyck@minres.com

Visibility
Publicly available!
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