Image

Moonlight is a subsystem around a TGC core developed by MINRES. The Good Core (TGC) [1] is a highly flexible, scalable and expandable RISC-V processor core and the TGC variant to be used in the subsystem is configurable.
Moonlight contains a configurable APB3 subsystem with a customizable number of different peripherals, e.g., GPIO, UART, Timer, SPI, I2S Receiver, DMA.
It features an AMBA-compatible high-speed bus connecting a memory system, a CPU, and an APB bridge. As optional additions, application-specific components as well as bridges to other bus systems can be integrated.
Visibility
Publicly available!
License
Send an email to eyck@minres.com
ISA Compliance
Status
Date of Availability
Contact
MINRES
Eyck Jentzsch
Keltenhof 2
85579 Neubiberg
Deutschland
Contact Email
eyck [at] minres.com
Asset Reference
Target TRL at the end of phase 1
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle
Component is required for safety critical systems
Nein
Category
RISC-V Subsystem