P - Packed-SIMD Instructions

muRISCV-NN

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muRISCV-NN Logo
Component is required for safety critical systems
Nein
Target TRL at the end of phase 1
TRL3: Nachweis der Funktionsfähigkeit --> Plattform ohne Parametrisierbarkeit
Target TRL at the end of phase 2
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung

We introduce muRISCV-NN, an open-source compute library for embedded and microcontroller class systems. muRISCV-NN targets to provide an open-source, and vendor-agnostic compute library targeting all RISC-V-compliant platforms for supplying a HW/SW interface between industry-standard deep learning libraries and emerging ultra-low-power compute platforms. Forked from ARM’s CMSIS-NN library, muRISCV-NN provides optimized scalar kernels written in plain C as an efficient and highly portable baseline.

Status
Visibility
Publicly available!

FreiTest

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FreiTest Logo
Component is required for safety critical systems
Ja
Target TRL at the end of phase 1
TRL4: Versuchsaufbau im Labor --> Plattform mit Parametrisierung
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle

FreiTest (developed from PHAETON) is an ATPG (Automatic Test Pattern Generation) Framework based on SAT-Solving (Boolean Satisfiability Problem) and BMC (Bounded Model Checking). It generates Test Patterns and Software-Based Self-Tests (SBSTs) for synthesized circuits and is under active development. First results on achieved Fault Coverages have been published on the IEEE ETS2023 conference in Venice under the title "Constraint-Based Automatic SBST Generation for RISC-V Processor Families".

Status
Visibility
Publicly available!