SCAIE-V Scalable ISA Extension Interface for RISC-V Cores
The SCAIE-V interface is a portable interface for extending RISC-V core with custom instructions. It applies to both pipelined and non-pipelined core. The custom instructions supported do not just cover Register-type instructions, but also extend to custom control flow (jumps, branches) and custom memory operations. SCAIE-V supports executing complex custom instructions more efficiently by decoupling their execution from the base processor, and automatically inserting the required hazard handling logic to guarantee their correct interoperation with regular RISC-V instructions.
Apache 2.0
UltraTrail - Ultralow-Power AI Accelerator for Edge Devices
UltraTrail is a configurable hardware accelerator for real-time inference of temporal convolutional networks (TCNs) on edge devices. Designed for near-sensor signal processing on energy-constrained platforms it features an optimized dataflow for one-dimensional convolution with a total power consumption in the low microwatt range. The parameterizable architecture combined with a hardware-aware neural architecture search (NAS) allows an automatic generation of domain-specific accelerator instances. Accurate models for power, performance, and area enable a fast design-space exploration.