TGC Cores

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TGC Core

The Good Folk Series is a highly flexible, scalable and configurable RISC-V based core family developed by MINRES. The standard cores can easily be tailored to specific application requirements using CoreDSL.

It is technology independent, ensures integrity and targets low power edge computing applications. The comprehensive SDK and concise documentation makes it accessible to small and medium companies.

The core family is developed with ASIL readiness criteria in mind, as an ISO 26262 certifiable out-of-context IP, where the pertinent functional safety documentation is available.

There are five cores available:

TGC5A - RV32E, 3 stages, 16 registers, for state machine controllers
TGC5B - RV32I, 3 stages, 32 registers, for embedded systems
TGC5C - RV32IMC, 4 stages, 32 registers, for IoT or edge applications
TGC5D - RV32IMC + CLIC, 4 stages, 32 registers, for IoT or edge applications with dense hw/sw coupling
TGC5E - RV32IMC + CLIC, 5 stages, 32 registers, for IoT or edge applications with high frequency requirements

Visibility
Publicly available!
License

Send an email eyck@minres.com

Supported Bus Protocols
Features
Status
Contact

MINRES
Eyck Jentzsch
Keltenhof 2
85579 Neubiberg
Deutschland

Contact Email
eyck [at] minres.com
Target TRL at the end of phase 1
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle
Target TRL at the end of phase 2
TRL7: Demonstration des Systemprototyps in einer betrieblichen Umgebung
Component is required for safety critical systems
Ja
Category
RISC-V Core