Not Applicable

Figure: Speculative program execution can enable side channel

Moonlight is a subsystem around a TGC core developed by MINRES. The Good Core (TGC) [1] is a highly flexible, scalable and expandable RISC-V processor core and the TGC variant to be used in the subsystem is configurable.

Moonlight contains a configurable APB3 subsystem with a customizable number of different peripherals, e.g., GPIO, UART, Timer, SPI, I2S Receiver, DMA.

The QEMU Timing Analyzer (QTA) is a QEMU plugin which extends QEMU for the time annotated execution of binary programs. QTA has been tested only for RISC-V and TriCore. As the implementation extends QEMU through TCG plugin API it should be compatible with any other ISA and all future QEMU versions . QTA comes with a frontend that can import output files from AbsInt aiT WCET analysis.

The eVerify framework supports formal software verification by considering the hardware behavior of loosely coupled devices, e.g., peripherals.

This is achieved using the Behavioral Description (BD) based on CTL* to specify hardware behavior from the software point of view. Based on the BD specification, the tool verifyDown generates assumptions/assertions for the hardware description and the software driver code.

The CDR is a an analog ecosystem component that implements in a high speed serial data input interface. The CDR extracts clock information from the serial data stream and retimes the data. Combined with deserializers & serializers it provides high speed memory I/O access of several Gbps. In first designs the CDR applies NRZ coding validated in 22FDX and IHP 130nm technology. Later designs will be optimize for PAM4 encodings.

The PLL is a component of the Scale4Edge ecosystem that generates a high frequency clock output (>1 Ghz) from a low frequency clock input signal. The output frequency is a scalable multiple of the input frequency and configurable at runtime. The  PLL was designed with analog subcomponents in a first step. It will be optimized at system level as a synthesizable digital PLL in further steps. The designs are mainly validated by tapeouts in 22FDX technology.

While there exist many ways to deploy machine learning models on microcontrollers, it is non-trivial to choose the optimal combination of frameworks and targets for a given application.

Thus, automating the end-to-end benchmarking flow is of high relevance nowadays. MLonMCU allows performing complex benchmarks of edge ML workloads, frameworks and targets with minimal efforts

UMA (Universal Modular Accelerator Interface) is a unified infrastructure for easy integration of external hardware accelerators into the machine learning compiler framework TVM. UMA provides file structures, Python interface classes and a documented API and is available open-source in the latest releases of TVM.

Abbildung: Spekulative Programmausführung kann Seitenkanal ermöglichen

The SpiNNedge accelerator is designed for ultra-low-power processing and classification of time series from sensors in real time. It combines DSP functions for data preprocessing and feature extraction (frequency transforms, windowing, filtering, logarithm) with classification based on recurrent neural networks (RNN). The RNN module exploits sparsity for significantly reduced storage and processing effort. The accelerator performs individual processing layers autonomously. Complex layers can be flexibly assembled from base operations via a global control module.