Longnail High-Level Hardware Synthesis of Custom RISC-V Instructions

The Longnail High-Level Synthesis system translates abstract descriptions of the semantics of custom instructions formulated in CoreDSL 2.0 into actual hardware-blocks in RTL. 

CoreDSL 2.0 is styled after the C programming language, with which many embedded applications developers will be familiar. Longnail automatically performs the many steps that would be required to translate such an algorithmic into efficient hardware, including optimized scheduling, resource sharing, memory block selection etc. It targets the SCAIE-V interface, also created in Scale4Edge, and is thus portable to all processors on which SCAIE-V is supported. This currently ranges from small MCU-class cores up to Linux-capable application class cores such as the OpenHWGroup's CVA6.

The resulting hardware block is exported as RTL in SystemVerilog and can then be passed on to traditional ASIC design tools for further processing.

Longnail will be licensed to MINRES Technologies GmbH for commercial use. Academic research-only users should also contact the company for specialized licenses.