FreiTest (developed from PHAETON) is an ATPG (Automatic Test Pattern Generation) Framework based on SAT-Solving (Boolean Satisfiability Problem) and BMC (Bounded Model Checking). It generates Test Patterns and Software-Based Self-Tests (SBSTs) for synthesized circuits and is under active development. First results on achieved Fault Coverages have been published on the IEEE ETS2023 conference in Venice under the title "Constraint-Based Automatic SBST Generation for RISC-V Processor Families".

Generate tflite micro code which bypasses the interpreter (directly calls into kernels)

Basically this code uses a fully set up tflite micro instance to dump the internal allocations and function calls assigned to the model, then dumps the tensor and node settings into a compilable file, eliminating the need for running the interpreter at each program start and for resolving the correct kernel at run time.

PikeOS and PikeOS for MPU are each a real-time operating system and hypervisor for embedded systems. It provides partitioning to separate different applications or guest operating systems from each other. PikeOS is often combined with ELinOS, SYSGO's embedded Linux, which is then run in a partition under the PikeOS hypervisor.

Instruction Set Architecture eXtensions (here abbreviated as ISAX), sometimes also known as Custom Instructions, are one of the key means to specialize a processor for a specific application domain. They enable, e.g., higher performance or better energy efficiency than realizing the applications using just the generic, general-purpose instruction set.

In Scale4Edge, TUDA works on three key technologies aiming to ease the development and deployment of ISAX:

The Extensible Compiler provides an LLVM-based toolchain to develop C/C++/Assembly programs for RISC-V. It is designed to easily accommodate custom extensions to the RISC-V ISA by supporting the Scale4Edge developed CoreDSL for describing ISA extensions.

UltraTrail is a configurable hardware accelerator for real-time inference of temporal convolutional networks (TCNs) on edge devices. Designed for near-sensor signal processing on energy-constrained platforms it features an optimized dataflow for one-dimensional convolution with a total power consumption in the low microwatt range. The parameterizable architecture combined with a hardware-aware neural architecture search (NAS) allows an automatic generation of domain-specific accelerator instances. Accurate models for power, performance, and area enable a fast design-space exploration.

aiT automatically computes safe bounds for the worst-case execu­tion time of tasks in bina­ry execut­ables, taking into account the cache and pipe­line behavior of the processor in question.

StackAnalyzer automatically determines the worst-case stack usage of the tasks in embed­ded applications. It directly ana­lyzes binary execut­ables and considers all possible execution scenarios.

Based on years of experience developing and integrating SystemC based virtual platforms in the industry, MINRES has created DBT-RISE (Dynamic Binary Translation Re-targetable Instruction Set Simulator), a versatile environment to rapidly implement ISS of any architecture. DBT-RISE serves as basis for the implementation of the TGC (The Good Core) ISS (TGC-VP).

TGC-VP provides the following features:

The Good Folk Series is a highly flexible, scalable and configurable RISC-V based core family developed by MINRES. The standard cores can easily be tailored to specific application requirements using CoreDSL.

It is technology independent, ensures integrity and targets low power edge computing applications. The comprehensive SDK and concise documentation makes it accessible to small and medium companies.

An extensible and configurable RISC-V based Virtual Prototype (VP) implemented in SystemC TLM. The feature set includes support for the RV32GC and RV64GC ISA, privilege levels (M,S,U), virtual memory, SW debug via Eclipse, a HiFive1 configuration and several operating systems including Linux. At UB the RISC-V VP serves as platform for several different research directions (visit https://agra.informatik.uni-bremen.de/projects/risc-v/ for further information and the most recent updates).