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R4VES is an automation and configuration tool for simulating RISC-V Software-based Self-Tests (SBST) using different fault models (Stuck-At- / Transition-Delay- and Cell-Aware Faults).

Cell-Aware SPICE Simulation is a tool to simulate defects in library cells to generate cell-aware fault models.

Reconfigurable Scan-Network Insertion is a tool for creation and insertion of Reconfigurable Scan Networks (RSN) with flexible configurations and structural circuit modifications.

Decoder and tracer for RISC-V E-Traces

This library provides a decoder and a tracer for the instruction tracing defined in the Efficient Trace for RISC-V specification. It provides:

The SCAIE-V interface is a portable interface for extending RISC-V core with custom instructions. It applies to both pipelined and non-pipelined core. The custom instructions supported do not just cover Register-type instructions, but also extend to custom control flow (jumps, branches) and custom memory operations. SCAIE-V supports executing complex custom instructions more efficiently by decoupling their execution from the base processor, and automatically inserting the required hazard handling logic to guarantee their correct interoperation with regular RISC-V instructions.

Moonlight is a subsystem around a TGC core developed by MINRES. The Good Core (TGC) [1] is a highly flexible, scalable and expandable RISC-V processor core and the TGC variant to be used in the subsystem is configurable.

Moonlight contains a configurable APB3 subsystem with a customizable number of different peripherals, e.g., GPIO, UART, Timer, SPI, I2S Receiver, DMA.

The QEMU Timing Analyzer (QTA) is a QEMU plugin which extends QEMU for the time annotated execution of binary programs. QTA has been tested only for RISC-V and TriCore. As the implementation extends QEMU through TCG plugin API it should be compatible with any other ISA and all future QEMU versions . QTA comes with a frontend that can import output files from AbsInt aiT WCET analysis.

We introduce muRISCV-NN, an open-source compute library for embedded and microcontroller class systems. muRISCV-NN targets to provide an open-source, and vendor-agnostic compute library targeting all RISC-V-compliant platforms for supplying a HW/SW interface between industry-standard deep learning libraries and emerging ultra-low-power compute platforms. Forked from ARM’s CMSIS-NN library, muRISCV-NN provides optimized scalar kernels written in plain C as an efficient and highly portable baseline.

The Ecosystem microcontroller is a PULPissimo-based microcontroller featuring the following Scale4Edge ecosystem IPs:

• A RISC-V TGC processor core
• The AI hardware accelerator UltraTrail
• A phase-locked loop (PLL)

Due to the high configurability of the individual components, the platform can be quickly and easily adapted to specific applications. A specialized ecosystem microcontroller was taped-out in 22nm FDSOI technology as a demonstrator for an audio event detection use-case provided by the project partner Bosch.

An RTL processor implementation can be verified using our co-simulation approaches, which compares the implementation with a functional reference model. As a functional reference model, an instruction set simulator (ISS) that is part of the open-source RISC-V VP can be used. Our cross-level processor verification approach generates endless instruction streams and tightly integrates the ISS with the RTL core with the aid of in-memory communication. The setup allows restriction-free instruction generation, enabling a comprehensive testing approach.