In progress

Moonlight is a subsystem around a TGC core developed by MINRES. The Good Core (TGC) [1] is a highly flexible, scalable and expandable RISC-V processor core and the TGC variant to be used in the subsystem is configurable.

Moonlight contains a configurable APB3 subsystem with a customizable number of different peripherals, e.g., GPIO, UART, Timer, SPI, I2S Receiver, DMA.

The eVerify framework supports formal software verification by considering the hardware behavior of loosely coupled devices, e.g., peripherals.

This is achieved using the Behavioral Description (BD) based on CTL* to specify hardware behavior from the software point of view. Based on the BD specification, the tool verifyDown generates assumptions/assertions for the hardware description and the software driver code.

The CDR is a an analog ecosystem component that implements in a high speed serial data input interface. The CDR extracts clock information from the serial data stream and retimes the data. Combined with deserializers & serializers it provides high speed memory I/O access of several Gbps. In first designs the CDR applies NRZ coding validated in 22FDX and IHP 130nm technology. Later designs will be optimize for PAM4 encodings.

The PLL is a component of the Scale4Edge ecosystem that generates a high frequency clock output (>1 Ghz) from a low frequency clock input signal. The output frequency is a scalable multiple of the input frequency and configurable at runtime. The  PLL was designed with analog subcomponents in a first step. It will be optimized at system level as a synthesizable digital PLL in further steps. The designs are mainly validated by tapeouts in 22FDX technology.

FreiTest (developed from PHAETON) is an ATPG (Automatic Test Pattern Generation) Framework based on SAT-Solving (Boolean Satisfiability Problem) and BMC (Bounded Model Checking). It generates Test Patterns and Software-Based Self-Tests (SBSTs) for synthesized circuits and is under active development. First results on achieved Fault Coverages have been published on the IEEE ETS2023 conference in Venice under the title "Constraint-Based Automatic SBST Generation for RISC-V Processor Families".