ETISS - Extendable Translating Instruction Set Simulator
ETISS is a C++ ISS (Instruction Set Simulator), which is designed to simulate instructions for a target core on a host computer. It translates binary instructions into C code and appends translated code into a block, which will be compiled and executed at runtime. As aforementioned, it is Extendable, thus it supports myriad level of customization by adopting the technique of plug-ins. ETISS supports varied Instruction Set Architectures (ISAs) according to user needs (see architecture models in ArchImpl/
).
See file LICENSE inside GitHub Repo.
StarVision PRO - Debugging Cockpit for Transistor, RTL, and System-Level Designs
StarVision® PRO represents the state-of-the-art in debug solutions for advanced electronic SoCs. The incorporation of Concept's leading visualization and detection technology enables rapid cause-effect analysis for efficient functional analysis. This advanced and unique mixed-mode debug platform seamlessly combines SPICE and transistor analysis from our market leading SpiceVision PRO tool with digital RTL and gates from our advanced RTLvision PRO tool.
For access to the tool, send an e-mail to info@concept.de with remark "Scale4Edge".
CompCert - Formally verified C compiler
CompCert is a formally verified optimizing C compiler. It accepts most of the ISO-C 99 language, with some minor exceptions and a few useful extensions. Its intended use is the compilation of life-critical and mission-critical software written in C and meeting high levels of assurance.
This distribution of CompCert can be used for evaluation and research, but not for commercial purposes (see also the license information in the installation packages). Commercial licenses can be obtained from AbsInt.