An RTL processor implementation can be verified using our co-simulation approaches, which compares the implementation with a functional reference model. As a functional reference model, an instruction set simulator (ISS) that is part of the open-source RISC-V VP can be used. Our cross-level processor verification approach generates endless instruction streams and tightly integrates the ISS with the RTL core with the aid of in-memory communication. The setup allows restriction-free instruction generation, enabling a comprehensive testing approach.

SymEx-VP focuses explicitly on testing software for constrained embedded devices (e.g. as used in the Internet of Things). This software often interacts very closely with low-level hardware peripherals and in order to support these interactions, during simulation-based software testing, SymEx-VP supports SystemC peripheral models. SystemC is a C++ class library for modeling hardware peripherals.

While there exist many ways to deploy machine learning models on microcontrollers, it is non-trivial to choose the optimal combination of frameworks and targets for a given application.

Thus, automating the end-to-end benchmarking flow is of high relevance nowadays. MLonMCU allows performing complex benchmarks of edge ML workloads, frameworks and targets with minimal efforts

UMA (Universal Modular Accelerator Interface) is a unified infrastructure for easy integration of external hardware accelerators into the machine learning compiler framework TVM. UMA provides file structures, Python interface classes and a documented API and is available open-source in the latest releases of TVM.

FEAR-V is a fast scalable simulation and analysis framework for RISC-V architectures based on QEMU. The generation, simulation, and analysis can be scaled by ISA configuration as well as n-bit permanent and transient faults. The fault injection covers GPR, CSR, instruction, and memory analysis.

Abbildung: Spekulative Programmausführung kann Seitenkanal ermöglichen

The SpiNNedge accelerator is designed for ultra-low-power processing and classification of time series from sensors in real time. It combines DSP functions for data preprocessing and feature extraction (frequency transforms, windowing, filtering, logarithm) with classification based on recurrent neural networks (RNN). The RNN module exploits sparsity for significantly reduced storage and processing effort. The accelerator performs individual processing layers autonomously. Complex layers can be flexibly assembled from base operations via a global control module.

The HighRel Multiprocessor is a Pulpissimo-based quad-core processing system that is specifically built to withstand the harsh environments as they occur in avionics or astronautics. Based on the required processing power as well as different health and environmental monitors, the system is able to autonomously configure itself to various states of fault tolerance (DMR, TMR or QMR) or performance (low power or high performance).

Concept Engineering's Nlview® engine provides automatic generation of schematic diagrams for different levels of electronic circuits, including gate-level, RTL and block-level. Optional engines are available for the system-level (S-engine), for the transistor-level (T-engine), and for automotive and aerospace applications (E-engine).

The CHIPS Verification Framework is a collection of tools and libraries for (formal) hardware design verification. The framework encompasses two subprojects:

CHIPS: Chisel Hardware Property Specification Language

The foundation of the CHIPS-VF is a domain-specific language (DSL) embedded in Scala that allows the specification of lightweight verification properties on different levels of abstraction using the assertion-based verification paradigm.