On Chip Debug Hardware

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RISC-V Debug System Overview - Source: Figure 2.1 in RISC-V External Debug Support Version 0.13.2 (https://riscv.org/technical/specifications/)
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RISC-V Debug System Overview (Source: Figure 2.1 in RISC-V External Debug Support Version 0.13.2)

Infineon implements for its evaluation platform in alignment with Partner Lauterbach specific Hardware Components for On-Chip-Debug. The Hardware acts as Evaluation Vehicle for the Lauterbach On Chip Debug solution.

Visibility
Internal for Scale4Edge partners only!
License

The Infineon Solution will be productized with its chips. It is therefore no tool or IP but part of semiconductor products.

ISA Compliance
Debug Support - Privileged Level 4
RV32I - Base Integer, 32-bit
RV32E - Base Integer (embedded), 32-bit
A - Atomic Instructions
C - Compressed Instructions
M - Multiplication / Division
N - User-Level Interrupts
Zicsr - Control and Status Register (CSR)
User (U-mode, lowest privileges)
Supported Bus Protocols
AHB3
AHB3 Light
AXI4
Status
Planned
Date of Availability
Contact

Infineon Technologies
Wolfgang Ecker
Am Campeon 1-15
85579 Neubiberg
Deutschland

Contact Email
wolfgang.ecker [at] infineon.com
Contact Phone
+498923445334
Target TRL at the end of phase 1
TRL5: Versuchsaufbau in vereinfachter Einsatzumgebung --> Optimierte Plattform
Target TRL at the end of phase 2
TRL6: Prototyp in vereinfachter/simulierter Einsatzumgebung --> Anwendungsfälle
Component is required for safety critical systems
Nein