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The SpiNNedge accelerator is designed for ultra-low-power processing and classification of time series from sensors in real time. It combines DSP functions for data preprocessing and feature extraction (frequency transforms, windowing, filtering, logarithm) with classification based on recurrent neural networks (RNN). The RNN module exploits sparsity for significantly reduced storage and processing effort. The accelerator performs individual processing layers autonomously. Complex layers can be flexibly assembled from base operations via a global control module.

The HighRel Multiprocessor is a Pulpissimo-based quad-core processing system that is specifically built to withstand the harsh environments as they occur in avionics or astronautics. Based on the required processing power as well as different health and environmental monitors, the system is able to autonomously configure itself to various states of fault tolerance (DMR, TMR or QMR) or performance (low power or high performance).

Altair Engineering's Nlview® engine provides automatic generation of interactive schematic diagrams for different levels of electronic circuits, including gate-level, RTL and block-level. Optional engines are available for the system-level (S-engine), for the transistor-level (T-engine), and for automotive and aerospace applications (E-engine).

The CHIPS Verification Framework is a collection of tools and libraries for (formal) hardware design verification. The framework encompasses two subprojects:

CHIPS: Chisel Hardware Property Specification Language

The foundation of the CHIPS-VF is a domain-specific language (DSL) embedded in Scala that allows the specification of lightweight verification properties on different levels of abstraction using the assertion-based verification paradigm.

Extended CIRCT Hardware Compiler

Lauterbach implements debugging and trace support in alignment with Partner Infineon specific Hardware Solution. 

Infineon implements for its evaluation platform in alignment with Partner Lauterbach specific Hardware Components for On-Chip-Debug. The Hardware acts as Evaluation Vehicle for the Lauterbach On Chip Debug solution.

FreiTest (developed from PHAETON) is an ATPG (Automatic Test Pattern Generation) Framework based on SAT-Solving (Boolean Satisfiability Problem) and BMC (Bounded Model Checking). It generates full-scan / sequential test patterns and Software-Based Self-Tests (SBSTs) for synthesized circuits using the Validity Checker Module (VCM) specification mechanism.

Generate tflite micro code which bypasses the interpreter (directly calls into kernels)

Basically this code uses a fully set up tflite micro instance to dump the internal allocations and function calls assigned to the model, then dumps the tensor and node settings into a compilable file, eliminating the need for running the interpreter at each program start and for resolving the correct kernel at run time.

PikeOS and PikeOS for MPU are each a real-time operating system and hypervisor for embedded systems. It provides partitioning to separate different applications or guest operating systems from each other. PikeOS is often combined with ELinOS, SYSGO's embedded Linux, which is then run in a partition under the PikeOS hypervisor.