R4VES is an automation and configuration tool for simulating RISC-V Software-based Self-Tests (SBST) using different fault models (Stuck-At- / Transition-Delay- and Cell-Aware Faults).

NCIP is a Bounded Model Checker (BMC) for solving formal problems in various input formats (AIGER / CNF). Using Craig interpolants it is able to prove unreachability for some formal problems that can be validated via generated unreachability certificates.

Cell-Aware SPICE Simulation is a tool to simulate defects in library cells to generate cell-aware fault models.

Reconfigurable Scan-Network Insertion is a tool for creation and insertion of Reconfigurable Scan Networks (RSN) with flexible configurations and structural circuit modifications.

Decoder and tracer for RISC-V E-Traces

This library provides a decoder and a tracer for the instruction tracing defined in the Efficient Trace for RISC-V specification. It provides:

The Longnail High-Level Synthesis system translates abstract descriptions of the semantics of custom instructions formulated in CoreDSL 2.0 into actual hardware-blocks in RTL. 

The SCAIE-V interface is a portable interface for extending RISC-V core with custom instructions. It applies to both pipelined and non-pipelined core. The custom instructions supported do not just cover Register-type instructions, but also extend to custom control flow (jumps, branches) and custom memory operations. SCAIE-V supports executing complex custom instructions more efficiently by decoupling their execution from the base processor, and automatically inserting the required hazard handling logic to guarantee their correct interoperation with regular RISC-V instructions.

Figure: Speculative program execution can enable side channel

Moonlight is a subsystem around a TGC core developed by MINRES. The Good Core (TGC) [1] is a highly flexible, scalable and expandable RISC-V processor core and the TGC variant to be used in the subsystem is configurable.

Moonlight contains a configurable APB3 subsystem with a customizable number of different peripherals, e.g., GPIO, UART, Timer, SPI, I2S Receiver, DMA.

The QEMU Timing Analyzer (QTA) is a QEMU plugin which extends QEMU for the time annotated execution of binary programs. QTA has been tested only for RISC-V and TriCore. As the implementation extends QEMU through TCG plugin API it should be compatible with any other ISA and all future QEMU versions . QTA comes with a frontend that can import output files from AbsInt aiT WCET analysis.