PLL (Phase Locked Loop) ecosystem component

The PLL is a component of the Scale4Edge ecosystem that generates a high frequency clock output (>1 Ghz) from a low frequency clock input signal. The output frequency is a scalable multiple of the input frequency and configurable at runtime. The  PLL was designed with analog subcomponents in a first step. It will be optimized at system level as a synthesizable digital PLL in further steps. The designs are mainly validated by tapeouts in 22FDX technology.