Verification IP

An RTL processor implementation can be verified using our co-simulation approaches, which compares the implementation with a functional reference model. As a functional reference model, an instruction set simulator (ISS) that is part of the open-source RISC-V VP can be used. Our cross-level processor verification approach generates endless instruction streams and tightly integrates the ISS with the RTL core with the aid of in-memory communication. The setup allows restriction-free instruction generation, enabling a comprehensive testing approach. The instruction streams are dynamically evolved at runtime through a feedback loop utilizing the observed coverage information. Moreover, the novel concept of coverage-guided aging can be employed to improve the coverage distribution over time. As an alternative, the instruction stream can also be generated by using coverage-guided fuzzing, a popular software-domain verification technique. The fuzzing process can be further enhanced using custom mutation procedures for typical instruction pattern generation. These cross-level processor verification approaches can be further extended using symbolic execution, another promising technique of the SW domain. It is a formal verification technique that uses symbolic expressions to represent concrete values.