Not Applicable

R4VES is an automation and configuration tool for simulating RISC-V Software-based Self-Tests (SBST) using different fault models (Stuck-At- / Transition-Delay- and Cell-Aware Faults).

NCIP is a Bounded Model Checker (BMC) for solving formal problems in various input formats (AIGER / CNF). Using Craig interpolants it is able to prove unreachability for some formal problems that can be validated via generated unreachability certificates.

Cell-Aware SPICE Simulation is a tool to simulate defects in library cells to generate cell-aware fault models.

Reconfigurable Scan-Network Insertion is a tool for creation and insertion of Reconfigurable Scan Networks (RSN) with flexible configurations and structural circuit modifications.

Decoder and tracer for RISC-V E-Traces

This library provides a decoder and a tracer for the instruction tracing defined in the Efficient Trace for RISC-V specification. It provides:

Figure: Speculative program execution can enable side channel

Moonlight is a subsystem around a TGC core developed by MINRES. The Good Core (TGC) [1] is a highly flexible, scalable and expandable RISC-V processor core and the TGC variant to be used in the subsystem is configurable.

Moonlight contains a configurable APB3 subsystem with a customizable number of different peripherals, e.g., GPIO, UART, Timer, SPI, I2S Receiver, DMA.

The QEMU Timing Analyzer (QTA) is a QEMU plugin which extends QEMU for the time annotated execution of binary programs. QTA has been tested only for RISC-V and TriCore. As the implementation extends QEMU through TCG plugin API it should be compatible with any other ISA and all future QEMU versions . QTA comes with a frontend that can import output files from AbsInt aiT WCET analysis.

The eVerify framework supports formal software verification by considering the hardware behavior of loosely coupled devices, e.g., peripherals.

This is achieved using the Behavioral Description (BD) based on CTL* to specify hardware behavior from the software point of view. Based on the BD specification, the tool verifyDown generates assumptions/assertions for the hardware description and the software driver code.

The CDR is a an analog ecosystem component that implements in a high speed serial data input interface. The CDR extracts clock information from the serial data stream and retimes the data. Combined with deserializers & serializers it provides high speed memory I/O access of several Gbps. In first designs the CDR applies NRZ coding validated in 22FDX and IHP 130nm technology. Later designs will be optimize for PAM4 encodings.